The Intel 386 CPU, a relic of the late-1980s, may seem like an outdated component today, but its engineering is still fascinating. Ken Shirriff used a CT scanner to explore the intricate pin mapping, hidden power planes, and other intricacies of this classic CPU without touching it.
The scan produced hundreds of X-ray slices, which were stitched into a 3D model that can be spun, zoomed, and digitally “peeled” layer by layer. The first reveal is a halo of gold bond wires radiating from the silicon die, acting as microscopic suspension bridges between the die’s pads and the package’s internal routing.
The 386’s package shows its true sophistication: it’s essentially a six-layer circuit board in miniature, with two internal layers carrying signals and four dedicated copper planes delivering clean power and ground. This “single-row double-shelf” bonding method was used to cram maximum connectivity into a compact footprint.
Digging deeper, Shirriff mapped which pins connect where, some routing directly to I/O pads, while others are buried deep in the power and logic supply network. The CT imaging even caught details Intel probably never intended anyone to see, like fine side wires used during manufacturing to electroplate the pins in gold.
Moving on, the scans compare the signal and power layers side-by-side, revealing the design’s sophistication. The signal layers are intricate and precise, designed to navigate complex logic inside, while the power layers deliver clean, steady power and ground, making sure everything runs smoothly without interference or noise.
The packaging acts like a bridge across massive differences in scale, from microscopic features on the silicon die to bulky socket pins spaced 2.54 millimeters apart. The CT scan work doesn’t just satisfy curiosity but is a reminder of Intel’s engineering investment in what seemed like mundane aspects – “the box it comes in.”
This innovation was pivotal in enabling performance leaps that made modern computing possible, and its packaging played a crucial role. Shirriff’s work provides a unique insight into the early microprocessor wars and Intel’s move to fully embrace high pin counts and advanced packaging.
Source: https://www.tomshardware.com/pc-components/cpus/ct-scan-peels-back-the-layers-of-time-to-reveal-the-engineering-within-intels-iconic-386-cpu-exposing-intricate-pin-mapping-hidden-power-planes-and-more